Complementary metal oxide semiconductor (CMOS) microprocessors typically comprise one or more integrated circuit (IC) chips. Each IC chip includes thousands and perhaps millions of n-type field effect transistors (NFETS) and p-type field effect transistors (PFETS) which are used to construct memory arrays, latches, and other combinatorial logic elements. These circuits must reliably store or process data during every microprocessor cycle (t.sub.cycle) over the lifetime (.delta.) of the microprocessor.
The term electromigration (EM) refers to the transport of mass in metals when stressed to high current densities. EM occurs during the passage of direct current (DC) through thin metal conductors in integrated semiconductor integrated circuits, and results in accumulation of metal in some regions and voids in other regions. EM in extreme cases may be catastrophic with respect to circuit performance if either (i) accumulations become so severe as to bridge adjacent conductors, thereby causing short circuits, or (ii) voids become so severe as to cause open circuits. Such occasions are referred to as catastrophic faults.
Less catastrophic results (intermittent faults), but nonetheless problematic, results are possible due to partial void formation. Partial void formation causes changes in the interconnection resistance between transistors in the microprocessor circuit over time (see, e.g. A van der Ziel, "Two Different Methods of Determining Electromigration Parameters Associated with Resistance Change", Solid State Electronics, Vol 33, No. 8, pp 1025-1027 (1990)). This time dependent interconnection resistance degradation (.DELTA.R.sub.int (.tau.))/R.sub.int is proportional to circuit propagation time degradation .DELTA.t.sub.pd (.tau.)/t.sub.pd, because the time it takes for signals to traverse the interconnection paths between interconnected transistors depends on the interconnection resistance. Accordingly, EM effects which degrade interconnection resistance also degrade circuit propagation time. The circuit propagation time degradation .DELTA.t.sub.pd (.tau.)/t.sub.pd, in turn, may result in intermittent timing-faults, and reduce microprocessor reliability over circuit lifetime (.delta.) (Krautschneider, et al., "Reliability Problems of Submicron MOS Transistors and Circuits", Microelectron Reliability, Vol 32, No. 11, pp 1499-1508, (1992)). Both time dependent interconnection resistance degradation (.DELTA.R.sub.int (.tau.))/R.sub.int, and circuit propagation time degradation .DELTA.t.sub.pd (.tau.)/t.sub.pd are dependent on manufacturing process variations, circuit design, and microprocessor application factors of temperature, voltage and lifetime.
The term hot-electron (HE) effect refers to the phenomenon of electrons which originate from FET surface channel currents, from impact ionization currents at the FET drain junction, or from substrate leakage currents. Electrons drifting from the gate may gain sufficient energy to enter into the gate, or they may collide with the silicon atoms and generate electron-hole pairs. The hole adds to substrate current, and the secondary electron may be injected into the gate of a subsequent FET (see e.g., M. Annaratone, H.B. Digital CMOS Circuit Design, Kluwer Academic Publishers, Norwell Mass., p. 39, (1986)). As these secondary electrons accumulate in the gate, the FET threshold voltage shifts and the internal resistance of the device changes. Device current I.sub.d is proportional to both the internal resistance of the device and (V.sub.GS -V.sub.T).sup.2. Therefore, as the threshold voltage V.sub.T and the internal resistance changes, the current drive capability I.sub.d of the device changes. This time dependent, drain current degradation .DELTA.I.sub.d (.tau.)/I.sub.d must be less than 0.1 according to conventional hot-electron reliability criteria.
Drain current degradation .DELTA.I.sub.d (.tau.)/I.sub.d is a wear-out effect which reduces circuit reliability, because it also causes changes in circuit propagation time .DELTA.t.sub.pd (.tau.), which may result in intermittent timing-faults. Variances in the circuit propagation time, .DELTA.t.sub.pd (.tau.)/t.sub.pd, which are caused by this hot electron-induced drain current degradation effect, and the resulting changes in device internal resistance, are proportional to the time dependent drain current degradation .DELTA.I.sub.d (.tau.)/I.sub.d, which reduces microprocessor reliability over circuit lifetime (.delta.). Time dependent drain current degradation .DELTA.I.sub.d (.tau.)/I.sub.d and circuit propagation time degradation .DELTA.t.sub.pd (.tau.)/t.sub.pd are dependent on manufacturing process variations, circuit design, and microprocessor application factors of temperature, voltage and lifetime.
The hot electron and EM effects on propagation degradation are considered during circuit level design for each transistor (hot electron effect) and each transistor interconnect (EM effect) (see, e.g.T.J. O'Gorman, ADCHECK Circuit Reliability Program, IBM Microelectronics Division, May, 1994). The problem is that circuit-level analysis does not include the manner in which hot electron and EM effects are subsequently influenced by fabrication process variation, global wiring, and application factors such as temperature, voltage, and lifetime, or how these factors would be combined to optimize parametric yield.
Accordingly, when assessing microprocessor reliability, circuit designers must attempt to determine time dependent interconnection resistance degradation .DELTA.R.sub.int (.tau.))/R.sub.int, as well as time dependent drain current degradation .DELTA.I.sub.d (.tau.)/I.sub.d. Because both of these terms are proportional to variances in circuit propagation time .DELTA.t.sub.pd (.tau.)/t.sub.pd, the circuit designer may assess both interconnection resistance degradation and drain current degradation by analyzing .DELTA.t.sub.pd (.tau.)/t.sub.pd. Circuit propagation time degradation which is caused by EM and hot electron effects may then be used to determine if a particular circuit satisfies established timing criteria. In doing so, designers insure proper timing and amplitude of data and control signals propagating through the circuit, by insuring that the microprocessor may tolerate circuit propagation time degradation .DELTA.t.sub.pd (.tau.)/t.sub.pd caused by both electromigration and hot electron effects.